Nowaday microprocessors require fast programmable and fast readable memory devices (among others EEPROMs). In conventional EPROM memory devices, the programming mechanism is based on a channel hot electron injection mechanism. In order to program a transistor memory cell high voltages should be applied to the gate and the drain of the transistor. This results in a high power consumption to program the device.
Flash memories were devised to combine the higher densities and faster programming techniques of EPROMs with the electrical erasability and in-circuit reprogrammability of EEPROMs. Flash EEPROMs are at present mainly used as a substitute for EPROMs in products where in-circuit reprogrammability is important. The main applications are expected in the field of computers and telecommunication, although also the use in automotive and defence sectors is expected to become more important than today. Moreover, flash EEPROM also has the potential to become the technology of choice for new high volume applications such as solid state disks for portable computers (notebook and palmtop computers), portable phones, memory cards, storage media for cameras, and so on.
Most commercially available flash EEPROMs use Channel Hot Electron Injection (CHEI) for writing and Fowler-Nordheim (FN) tunneling through a thin oxide for erasure, although various alternative programming mechanisms have been proposed and implemented.
In "stacked-gate" devices which are based on ETOX technology, the flash EEPROM transistor is similar to the conventional double polysilicon EPROM structure but it uses a thinner gate oxide and a graded junction at the source to allow electrical erasure. The cell is still programmed with drain voltages larger than 5 V (in 1 .mu.m technology) and therefore requires an external voltage supply.
The high programming voltage and power consumption is a direct consequence of the low injection efficiency which is physically inherent to the conventional CHEI mechanism.
In recent publications, 5 V-only operation of this type of cell has been demonstrated but only from 0.6 .mu.m technologies on. At that point, 3.3 V-only operation should, however, already be considered. On the other hand, soft-write phenomena pose a severe reliability concern in these devices since the margin between the programming and read-out conditions becomes continuously smaller. The advantages of the ETOX cell are the small cell size and the fact that the cell can be implemented in existing EPROM designs and technologies. Indeed, only minor additional processing steps are required with respect to EPROM, while the programming conditions are almost identical to EPROM programming conditions.
Besides the need for an external power supply, the main disadvantages are imposed by overerase problems and short-channel effects such as drain turn-on and punch-through. Unlike the case of EPROM, where the UV-erase process is self-limiting, this is no longer the case when using electrical erasure. Since there is no select transistor present, this leads to severe problems when the device has been overerased to negative threshold voltages. Therefore, time and area consuming adaptive erasing procedures have to be implemented on the chip, which lead to higher design complexity.
A second approach is derived from the split-gate EPROM cell. These cells are again programmed by conventional CHEI at the drain, while erasure occurs either by FN tunneling through a thin oxide or by enhanced tunneling through a polyoxide layer.
The main advantage of this cell is that the presence of the series transistor makes it insensitive to overerase. Additionally, the split-gate structure is less sensitive to typical E(E)PROM short-channel effects. However, it still shows some of the disadvantages of the ETOX-concept, such as the need for an external power supply.
For the polyoxide version, (see, for example, U.S. Pat. No. 5,042,009 issued to Kazerounian et al.) 5 V-only operation has yet been achieved however at the expense of a milli-second-range programming time. In the thin oxide version, it becomes difficult to optimize the drain profile, since a graded profile is needed for erasure and a steep profile is necessary for optimal CHEI conditions. A bottleneck for this device was the fact that program and erase operations are performed at the same channel position, which leads to limited endurance.
Performing the erase operation through a polyoxide layer towards a separate erase gate could in fact remove these last two drawbacks but the polyoxide conduction mechanism requires very high erase voltages which are to be generated on chip and the number of write/erase cycles is known to be very limited. This can be solved by a gradual increase of the erase voltage, leading to even higher voltages.
Finally, in a third approach, a lot of effort has been spent in order to obtain a higher injection efficiency by means of Source Side Injection (SSI) techniques.
U.S. Pat. No. 4,794,565 discloses an alternative transistor structure which allows the programming operation to be performed using a low drain voltage and a high gate voltage. This known device includes an extra polysilicon gate that is located adjacent the stacked dual gate transistor structure above the diffused source region. A high lateral electric field is thereby generated adjacent the source when a high voltage is applied to the gate at the drain side of the device. Said lateral electric field combines with a high vertical field, resulting in a faster programming operation.
The concepts relying on this enhanced CHEI mechanism show a fast 5 V-only operation however at the expense of a considerably higher process complexity, at least in part due to the formation of the additional polysilicon gate. As a result, these devices are rather unsuited for low cost EEPROM technology and embedded applications.